A 56 Gb/s Analog PLL for Clock Recovery
نویسندگان
چکیده
We report on a clock-recovery circuit employing a phase locked loop (PLL) at 56.88 Gb/s demonstrated by locking to a 28.44 GHz sinosoidal signal while two additional circuits with adapted on-chip passive components locked to 29 Gb/s and 39 Gb/s pseudorandom bit sequences. To our knowledge, this is the first demonstration of an integrated PLL IC for clock recovery at a data rate well beyond 40 Gb/s.
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